It has been a long time since scaling design of LSI wiring aiming high integration of LSI has become world trend, but problems such as an increases in signal transmission delay and Joule loss due to an increase in wiring resistance and wiring disconnection/short-circuiting due to electro migration and the like have become apparent in the history of miniaturization of wiring, which has resulted in changes of materials to be used for wiring. In 1997, chips using copper (Cu) wirings as a wiring material instead of aluminum (Al) and aluminum alloy which have been used in LSIs until then appeared in the world, and the world has headed to development for putting a fine Cu wiring into practical use under the inspiration of the chips using Cu. Since the Cu wiring has features such as (1) low resistance, (2) high electro migration resistance, (3) high melting point, and the like, it is superior to the Al wiring regarding miniaturization, and application thereof to actual products has been expected for a long time. In addition, a wiring formation process such as wiring formation by utilizing chemical mechanical polishing (CMP) process and plating process have appeared in order to realize practical use of the Cu wiring and such a wiring formation process currently becomes one of processes generally inevitable for manufacturing. As an example of a semiconductor device having such a Cu wiring, there is a semiconductor device having a multi-layer Cu wiring structure.
On the other hand, as shown in Semiconductor Industry Association (SIA): ITRS (The International Technology Roadmap for Semiconductors) 2003, or Japan Electronics and Information Technology Industries Association's Semiconductor Technology Roadmap committee of Japan: International Semiconductor Technology Roadmap 2003 Edition (Japanese Translation), semiconductor Cu wiring being currently under development for commercialization is being shifting from 90 nm node to 45 nm node through 65 nm node according to the LSI wiring design rule by ITRS. A roadmap where the node reaching 45 nm to 32 nm after 2010 is also shown.
However, as scaling of wirings advances, as well as problems of reliability lowering in wirings caused by electro migration: EM and stress migration: SM have come to the front also in Cu wiring, as a problem on manufacturing technology, there has been a growing possibility that minute voids are formed on a surface of a wiring after CMP in the stage of manufacturing LSI, which can result in a critical void leading to wiring disconnection along with reduction of wiring width. Since such surface voids decrease yields resulting in a problem directly linked with manufacturing cost and performance, development of void-reducing technique is one of challenges essential in manufacturing to realize the wiring scaling.
In a manufacturing process of LSI associated with high integration as described above, the so-called damascene process where, after Cu is buried in an insulating layer previously formed with trenches by electroplating process, excessive Cu (overlay portion) other than Cu in trenches for wiring formation is removed using CMP so that wirings are formed has been put in practical use and spreading as a basic technique for microfabrication. Also, to the damascene process, a structure in which a barrier layer for preventing Cu diffusion from a Cu wiring to a silicon semiconductor and a seed layer of such as pure Cu or Cu alloy to serve as a seed for electroplating Cu wiring formation are applied to inside of a trench in an insulating layer has been generally adopted. Build-in elemental technologies for a wiring consistent with the wiring node as technologies to enable manufacture of LSI have been sequentially developed in the history of the Cu wiring manufacturing technique in each node width generation, for example, as read in Japanese Patent Application Laid-Open Publication No. 2001-068475 (Patent Document 1) and Japanese Patent Application Laid-Open Publication No. 2002-367999 (Patent Document 2).